lift-off process

    vendredi 08/01

    Litho 1st step

    New wafer batch 3481 rho>20kohm.cm
    In parallel, litho for bobin optimized on Si / SiO2 standard

    • Negative resist :
    bake wafer 1' @ 110°C (solvent evaporation)
    spin AZ5214E (per 16/12/2014) 60" @ 4krpm
    bake 1'30 @ 110°C
    Expo 31mJ/cm2 @ 365nm (2.8" @ 11mW), Vacuum contact
    bake 3' @ 120°C (=setpoint). (Increase time because resist perempted)
    Flood expo 27"
    Dev MIF726 50" @ 19.0°C, rinse ODI 60" beaker + 30" water tap
    • Residue removal
    30" ozone plasma @ 100W, 200µb
    
    lundi 11/01
    • Al evaporation
    - Ti pump, 5nm @ 0.2nm/s -> P_sas = 3.5e-8mb (cold)
    - Al 100nm @ 2nm/s, 5°, planetary 16°/s, P_ev ~ 6e-7mb
    • Lift-off
    warm aceton for as long as needed (typ. 1h) + few seconds US at minimal power 
     to get rid of last small residues
    

    On the wafer, 13 chips are dead (no bobin or open/shorted bobin), about 15 have only 1 resonator out of 2 or 4, and the rest is OK.

    Spin S1813 to protect
    Dice 3 chips from the bottom for resonator testing
    Clean in aceton

     


    Litho 2nd step

    mardi 19/01

    I put some BCB in the syringe as soon as possible to let all the possible bubbles go.   

    bake wafer 5' @ 110°C 
    spin AP3000 - 10" @ 500rpm acc 250rpm/s; 60" @ 6000rpm ; bake 1' @ 110°C
    spin BCB4024-40 - 10" @ 500rpm acc 250rpm/s; 60"@5000rpm ; bake 3'30 @90°C
    align layer 2 from mask with layer one 
    Expo 71mJ/cm2 @ 365nm, Vacuum contact -> 6.5" @ 11mW
    pre-bake wafer 30" @ 65°C before inmediate development
    Dev DS3000 at 31-32°C (very important) for 3min 30sec 
    (previous check with test waffers), rinse ODI 60" beaker + 30" water tap

    Result: NICE! Some bobines are missing. Were they all of them before?

    BPC6_1.PNGBPC6_2.PNG

    BPC6_4.PNG BPC6_5.PNG

    bake BPC6 wafer 1h @ 200°C

    I verify that the result is consistent with the motiv in the mask

    Capture.JPG


    Already done BCB cleaning??? -> check RIE notebook

    • BCB RIE cleaning
    SF6:O2 5:45, 250µb, 25W -> 70V, 35"
    

    Received a mask to open contact pads only before doing 3rd step

    Litho step 1b (contact pads)Modifier la section

    mercredi 23/03

    • spin

    The idea is to lithograph some square pads to etch and the deposit a Ti-Au cap layer. 

    bake wafer 5' @ 110°C 
    spin AZ5214E 60" @ 4000rpm acc 500rpm/s; bake 1' @ 110°C
    Align+Expo Layer1B 5" (47.5 mJ/cm2), Vacuum contact+Alignment Check
    bake 3' @ 120°C to crosslink exposed region
    Flood Expo 45" (427.5 mJ/cm2)
    Dev AZDeveloper:HDI 1:2 for 1min50sec (previous checks and temoin also), 
    rinse ODI 60" beaker + 30" water tap

    Result:

    2try-Layer2bis-1min50sec_02.JPG2try-Layer2bis-1min50sec_01.JPG

    • etch + evap
    Etch Ar 500V 130mA 1min40", planetary 16°/s, 0°
    Evap 20nm Ti @ 0.1nm/s, planetary 16°/s, 0°
    Evap 10nm Au @ 0.1nm/s, planetary 16°/s, 0°
    Lift-off Remover PG @70°C 
    Result:
    2try-Layer2bis-afterlifft_01.JPG2try-Layer2bis-afterlifft_02.JPG2try-Layer2bis-afterlifft_03.JPG
    2try-Layer2bis-afterlifft_04.JPG2try-Layer2bis-afterlifft_05.JPG2try-Layer2bis-afterlifft_06.JPG


    Litho 3rd step
    • LOR20B + AZ5214 processing
    bake the wafer @ 110°C for water removal
    spin TI prime @4krpm, bake 1min @110deg
    tape the wafer on blue clean room tape, cut to a ~3" size
    dispense 1-1.5mL resist slowly from a pipette (well centered on wafer)
    2" @ 300rpm acc 250rpm/s
    3" @ 800rpm acc 500rpm/s
    60" @ 1500rpm acc 500rpm/s
    Cut the edges of the spun resist on all sides of the wafer before untaping
    bake 5' @ 170 °C
    spin AZ5214 60" @ 4000rpm
    bake 1min @110deg
    Align+expo Layer3 dose 5" (47.5 mJ/cm2) +Vacuum contact +Alignment check.
    bake 3min @120deg
    flood expo 45"
    develop in AZ Developer 1:2 HDI 2min + rinse water + water tap
    develop in MF726 for 1min15sec (tabulated 1min10")

    Result:

    a good case and the worst case

    2ndcolumn_03.JPG3rdcolumn_05.JPG

    • clean
    Plasma O2 0.2mbar 100W 2min
    • evap
    TO CHECK:
    Etch Ar 500V 65mA 20", planetary 16°/s, 0°
    Evap 200nm Al @ 1nm/s, planetary 16°/s, 0°

    Litho 4th step
    • spin MAA / PMMA bilayer
    - spin MAA8.5 EL10 (batch 14020103, exp. 01/2015) @ 2000rpm for 60" + 2" @ 8000rpm acc 4k
    - bake hot plate setpoint 180°C, 5'
    - spin PMMA A4 (batch 12060427, exp. 7/1/2013) @ 4000rpm for 60"
    - bake hot plate setpoint 180°C, 15'
    - spin UV III (Vivien bottle) @ 4000rpm 60"
    - bake hot plate 140°C, 90"

    ellipso:
    MAA = 540 +/- 5nm

    PMMA = 170 +/- 10nm

    • dice

    Cut wafer in 2, and take 1/4

    • expo

    Expo Upper Left 1/4 on 20/05/2016
    30keV, dose pattern x1, dose undercut 0.25 (undercut boxes encompass main patterns), except for the feedback gate,  (test with main pattern at 1.2, no undercut)
    Have to exposed alignement marks and develop to have a chance to see them. Contrast is very bad!
    Dev 1' MIBK/IPA 1/3
    rinse 30" IPA

    • evap old plassys
    Pinit = 2e-7mb
    etch 500V, 5mA, 20", 0°
    Al 100nm @ 1nm/s
    
    • lift
    30min remover PG 70°C + pipette
    fresh remover 5" + US
    rinse ODI
    rinse IPA
    

    Litho 5th step
    • spin MAA / PMMA bilayer
    - spin MAA8.5 EL10 (batch 16030216, exp. 4/1/2017) 
        45" @ 2000rpm + 10" @ 8000rpm (acc. 4000rpm/s)
        from Philippe Campagne bottle, have to filter otherwise lots of tiny spots!
    - bake hot plate setpoint 180°C, 5'
    - spin PMMA A4 (batch 12060427, exp. 7/1/2013) 
        45" @ 4000rpm + 10" @ 8000rpm (acc. 4000rpm/s)
        from Vivien bottle
    - bake hot plate setpoint 180°C, 15'
    - spin UV III (Vivien bottle) @ 4000rpm 60"
    - bake hot plate 140°C, 90"

    Upper left 1/4th of the wafer processed on 23/05/2016

    ellipso:
    MAA = 495 - 515nm
    depending on position
    PMMA = 180 +/- 10nm

     

    • pre-dicing

    no cleave

    • expo step5a

    Expo on 25/05/2016 30keV, spot 1, 300µC/cm2
    open the small marks windows

    • cleave

    100% yield -> we have 6 processable chips + 3 test samples

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