SID1 - fabrication

SID1 - fabricationEdit

2015-11-16

Wafer high resistivity intrinsic Si <100>, 350 +/- 25µm, double side polished
deoxidation
HF: ODI 1:20, 1'
rinse ODI 1'

Evap 1st side
put clean room blue tape on the back side to avoid spoiling the surface
vacuum within 10' in old evaporator SPEC
1h pumping -> P = 5.2e-7mb (quite bad)
Al 102nm @ 1nm/s (Pev=9e-7mb!)

2015-11-17

Define the electrodes:
Resist process
S1813 @ 4krpm
bake 1' @ 110°C
exp 12" @ 13mW/cm^2
dev 1' (see bubbling starting from 50", indicating that the Al layer is being etched already)
rinse ODI

Etch
HF:ODI 1:20
on test sample, 15nm disappear optically in 5" -> 3nm/s on average, except that we have 5nm oxide which of course do not have the same etch rate
on true sample, the layer (less than 100nm) disappear optically in 25", let it 30" (-> between 3 and 4nm/s)

optical result: not really convenient, but still OK for a test of charge collection (all features are still very smooth)

Evap 2nd side
vacuum within 15' in old evaporator SPEC
put clean room blue tape on the electrodes side
overnight pumping
Al 101nm @ 1nm/s (Pev=7e-7mb)

TWO ISSUES:

• The printed transparent for the electrodes was not contrasted enough, so I had hard times making the mask out of it.
• The electrodes were not printed (from inkscape I think) at the proper scale!

meaning we have only 4 rings OK + 1 which is interrupted on the edge of the wafer (need to bond if we want to use it), and the 6th (outer) ring is not there.

Should be like that:                                                            How it is in fact: